? 2000 fairchild semiconductor corporation ds010580 www.fairchildsemi.com august 1989 revised august 2000 100302 low power quint 2-input or/nor gate 100302 low power quint 2-input or/nor gate general description the 100302 is a monolithic quint 2-input or/nor gate with common enable. all inputs have 50 k ? pull-down resistors and all outputs are buffered. features 43% power reduction of the 100102 2000v esd protection pin/function compatible with 100102 voltage compensated operating range = ? 4.2v to ? 5.7v available to industrial grade temperature range (plcc package only) ordering code: devices also available in tape and reel. specify by appending the suffix letter ?x? to the ordering code. connection diagrams 24-pin dip/soic 28-pin plcc pin descriptions order number package number package description 100302sc m24b 24-lead small outline integrated circuit (soic), jedec ms-013, 0.300 wide 100302pc n24e 24-lead plastic dual-in-line package (pdip), jedec ms-010, 0.400 wide 100302QC v28a 28-lead plastic lead chip carrier (plcc), jedec mo-047, 0.450 square 100302qi v28a 28-lead plastic lead chip carrier (plcc), jedec mo-047, 0.450 square industrial temperature range ( ? 40 c to + 85 c) pin names description d na ? d ne data inputs e enable input o a ? o e data outputs o a ? o e complementary data outputs
www.fairchildsemi.com 2 100302 logic symbol truth table h = high voltage level l = low voltage level d 1x d 2x e o x o x llllh llhhl lhlhl lhhhl hllhl hlhhl hhlhl hhhhl
3 www.fairchildsemi.com 100302 absolute maximum ratings (note 1) recommended operating conditions note 1: the ? absolute maximum ratings ? are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum rating. the ? recommended operating conditions ? table will define the conditions for actual device operation. note 2: esd testing conforms to mil-std-883, method 3015. commercial version dc electrical characteristics (note 3) v ee = ? 4.2v to ? 5.7v, v cc = v cca = gnd, t c = 0 c to + 85 c note 3: the specified limits represent the ? worst case ? value for the parameter. since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. conditions for testing sho wn in the tables are cho- sen to guarantee operation under ? worst case ? conditions. dip ac electrical characteristics v ee = ? 4.2v to ? 5.7v, v cc = v cca = gnd note 4: the propagation delay specified is for single output switching. delays may vary up to 100 ps with multiple outputs switching. storage temperature (t stg ) ? 65 c to + 150 c maximum junction temperature (t j ) + 150 c v ee pin potential to ground pin ? 7.0v to + 0.5v input voltage (dc) v ee to + 0.5v output current (dc output high) ? 50 ma esd (note 2) 2000v case temperature (t c ) commercial 0 c to + 85 c industrial ? 40 c to + 85 c supply voltage (v ee ) ? 5.7v to ? 4.2v symbol parameter min typ max units conditions v oh output high voltage ? 1025 ? 955 ? 870 mv v in = v ih(max) or v il(min) loading with v ol output low voltage ? 1830 ? 1705 ? 1620 mv 50 ? to ? 2.0v v ohc output high voltage ? 1035 mv v in = v ih(min) or v il(max) loading with v olc output low voltage ? 1610 mv 50 ? to ? 2.0v v ih input high voltage ? 1165 ? 870 mv guaranteed high signal for all inputs v il input low voltage ? 1830 ? 1475 mv guaranteed low signal for all inputs i il input low current 0.50 av in = v il(min) i ih input high current 240 av in = v ih(max) i ee power supply current ? 45 ? 36 ? 20 ma inputs open symbol parameter t c = 0 ct c = + 25 ct c = + 85 c units conditions min max min max min max t plh propagation delay 0.50 1.15 0.50 1.15 0.50 1.25 ns t phl data to output figures 1, 2 t plh propagation delay 0.70 1.90 0.70 1.90 0.80 2.00 ns (note 4) t phl enable to output t tlh transition time 0.40 1.20 0.40 1.20 0.40 1.20 ns figures 1, 2 t thl 20% to 80%, 80% to 20%
www.fairchildsemi.com 4 100302 commercial version (continued) soic and plcc ac electrical characteristics v ee = ? 4.2v to ? 5.7v, v cc = v cca = gnd note 5: the propagation delay specified is for single output switching. delays may vary up to 100 ps with multiple outputs switching. note 6: output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for any outputs w ithin the same pack- aged device. the specifications apply to any outputs switching in the same direction either high-to-low (t oshl ), or low-to-high (t oslh ), or in opposite directions both hl and lh (t ost ). parameters t ost and t ps guaranteed by design. symbol parameter t c = 0 ct c = + 25 ct c = + 85 c units conditions min max min max min max t plh propagation delay 0.50 1.05 0.50 1.05 0.50 1.15 ns t phl data to output figures 1, 2 t plh propagation delay 0.70 1.80 0.70 1.80 0.80 1.90 ns (note 5) t phl enable to output t tlh transition time 0.40 1.10 0.40 1.10 0.40 1.10 ns figures 1, 2 t thl 20% to 80%, 80% to 20% t oshl maximum skew common edge plcc only output-to-output variation 250 250 250 ps (note 6) data to output path t oshl maximum skew common edge plcc only output-to-output variation 310 310 310 ps (note 6) enable to output path t oslh maximum skew common edge plcc only output-to-output variation 200 200 200 ps (note 6) data to output path t oslh maximum skew common edge plcc only output-to-output variation 330 330 330 ps (note 6) enable to output path t ost maximum skew opposite edge plcc only output-to-output variation 250 250 250 ps (note 6) data to output path t ost maximum skew opposite edge plcc only output-to-output variation 330 330 330 ps ((note 6) enable to output path t ps maximum skew plcc only pin (signal) transition variation 200 200 200 ps (note 6) data to output path t ps maximum skew plcc only pin (signal) transition variation 280 280 280 ps (note 6) enable to output path
5 www.fairchildsemi.com 100302 industrial version plcc dc electrical characteristics (note 7) v ee = ? 4.2v to ? 5.7v, v cc = v cca = gnd, t c = ? 40 c to + 85 c note 7: the specified limits represent the ? worst case ? value for the parameter. since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. conditions for testing sho wn in the tables are cho- sen to guarantee operation under the ? worst case ? conditions. plcc ac electrical characteristics v ee = ? 4.2v to ? 5.7v, v cc = v cca = gnd note 8: the propagation delay specified is for single output switching. delays may vary up to 200 ps with multiple outputs switching. symbol parameter t c = ? 40 ct c = 0 c to + 85 c units conditions minmaxminmax v oh output high voltage ? 1085 ? 870 ? 1025 ? 870 mv v in = v ih(max) loading with v ol output low voltage ? 1830 ? 1575 ? 1830 ? 1620 or v il(min) 50 ? to ? 2.0v v ohc output high voltage ? 1095 ? 1035 mv v in = v ih(min) loading with v olc output low voltage ? 1565 ? 1610 or v il(max) 50 ? to ? 2.0v v ih input high voltage ? 1170 ? 870 ? 1165 ? 870 mv guaranteed high signal for all inputs v il input low voltage ? 1830 ? 1480 ? 1830 ? 1475 mv guaranteed low signal for all inputs i il input low current 0.05 0.05 av in = v il(min) i ih input high current 300 240 av in = v ih(max) i ee power supply current ? 45 ? 20 ? 45 ? 20 ma inputs open symbol parameter t c = ? 40 ct c = + 25 ct c = + 85 c units conditions minmaxminmaxminmax t plh propagation delay 0.40 1.05 0.50 1.05 0.50 1.15 ns figures 1, 2 (note 8) t phl data to output t plh propagation delay 0.70 1.80 0.70 1.80 0.80 1.90 ns t phl enable to output t tlh transition time 0.30 1.10 0.40 1.10 0.40 1.10 ns figures 1, 2 t thl 20% to 80%, 80% to 20%
www.fairchildsemi.com 6 100302 test circuitry notes: v cc , v cca = + 2v, v ee = ? 2.5v l1 and l2 = equal length 50 ? impedance lines r t = 50 ? terminator internal to scope decoupling 0.1 f from gnd to v cc and v ee all unused outputs are loaded with 50 ? to gnd c l = fixture and stray capacitance 3 pf figure 1. ac test circuit switching waveforms figure 2. propagation delay and transition times
7 www.fairchildsemi.com 100302 physical dimensions inches (millimeters) unless otherwise noted 24-lead small outline integrated circuit (soic), jedec ms-013, 0.300 wide package number m24b 24-lead plastic dual-in-line package (pdip), jedec ms-010, 0.400 wide package number n24e
www.fairchildsemi.com 8 100302 low power quint 2-input or/nor gate physical dimensions inches (millimeters) unless otherwise noted (continued) 28-lead plastic lead chip carrier (plcc), jedec mo-047, 0.450 square package number v28a fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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